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Workshop 5: From Algorithm to Silicon

Audio Development with AudioReachTM on Qualcomm Hardware

14:00 - 17:00 UTC | Monday 9th November 2026 | Conservatory
In-Person Only

The rapid integration of AI into audio processing has created a new class of challenges for audio developers. Modern Qualcomm System-on-Chip (SoC) platforms offer powerful heterogeneous compute resources — including the Hexagon DSP, CPU cores, and a dedicated embedded Neural Processing Unit — capable of running sophisticated AI-powered audio algorithms at remarkable power efficiency. However, harnessing these resources traditionally requires deep expertise in inter-process communication, shared memory management, interrupt handling, multi-core scheduling, and power state optimization — a skillset far removed from the audio signal processing domain where most audio developers live.

AudioReach, Qualcomm's open-source SDK, bridges this gap. By abstracting the complexity of heterogeneous hardware behind a familiar graph-based signal processing model, AudioReach allows audio developers to design, deploy, tune, and profile audio pipelines — including AI inference workloads — using concepts they already understand, without needing to become embedded systems or machine learning infrastructure experts. AudioReach is SoC agnostic and has been ported to platforms including Zephyr RTOS and Cadence DSP. This workshop provides a practical, hands-on introduction to AudioReach and its primary tooling — AudioReach Creator (ARC) — using real Qualcomm hardware and pre-built AI audio modules to demonstrate what is possible today.

Learning Objectives/Outcomes

  • Know how to use ARC to build, configure, deploy, and run AudioReach signal processing graphs on real hardware — including distributing workload across heterogeneous cores
  • Understand CAPI and how it enables any algorithm — C code, MATLAB-generated code, or AI model — to become a first-class AudioReach module deployable to the right core
  • Know how to profile an AudioReach pipeline in ARC — identifying bottlenecks, and making informed core assignment decisions
  • Have deployed a working audio pipeline on real Qualcomm hardware combining traditional DSP modules and an AI inference module in a single graph

Look forward to a structured 3-hour guided hands-on session combining short interactive presentations, live hardware demonstrations, and self-directed lab exercises.

Patrick Lai